Feedback loops in logic circuit design play a critical role in creating circuits that can change their behaviour based on previous outputs. A feedback loop occurs when the output of a circuit is looped back as an input to the same circuit. This is commonly seen in sequential logic circuits, such as flip-flops and counters, where the state of the circuit is dependent on its history.

Feedback loops can be used to create memory elements in a circuit, allowing the circuit to store and recall information. This is essential in building more complex computing elements like registers and memory cells. Feedback loops are also fundamental in designing oscillators and stabilising circuits, where the output needs to be controlled based on previous states to maintain a consistent behaviour.

However, careful design is required to ensure stability and avoid unwanted oscillations or race conditions, where the output fluctuates rapidly due to timing discrepancies within the circuit. The design of feedback loops thus requires a deep understanding of timing and propagation delays in circuits, as well as knowledge of how different components interact over time.

Software simulation for logic circuit design offers several advantages. Firstly, it allows for rapid prototyping and testing without the need for physical components, saving both time and resources. This is particularly useful in the initial stages of design, where changes are frequent. Simulations can accurately model the behaviour of a circuit, enabling designers to test and troubleshoot complex circuits efficiently. They also provide a safe environment to experiment with designs, which is crucial when working with high-voltage or sensitive components.

However, there are also disadvantages. Simulations can sometimes be imperfect, failing to account for real-world variables like power fluctuations, temperature changes, and physical wear and tear. This can lead to discrepancies between the simulated and actual performance of a circuit. Additionally, reliance on simulations can sometimes limit hands-on experience, which is vital for understanding the practical challenges and nuances of physical circuit design. Therefore, while simulations are a powerful tool, they should be complemented with physical prototyping, especially in the final stages of design.

Propagation delays are the time taken for an input change to produce a noticeable effect at the output of a logic gate. They are a critical factor in the design and functioning of logic circuits, especially in high-speed and complex systems.

Propagation delays can cause timing issues, particularly in sequential circuits where the timing of signals is crucial. If a signal arrives later than expected due to delays, it can lead to incorrect operations or glitches. This is particularly problematic in synchronous systems, where all operations are timed to a central clock signal. Delays can cause parts of the circuit to fall out of sync, leading to errors.

In designing logic circuits, engineers must account for these delays by ensuring that signals have enough time to propagate through the circuit before the next operation begins. This often involves setting an appropriate clock speed in synchronous systems or using asynchronous designs that don't rely on a single clock signal. Additionally, in very high-speed circuits, designers may use techniques like pipelining, where different stages of a circuit operate in parallel, to mitigate the effects of propagation delays.

A logic circuit designer might choose to use a NOR gate instead of an OR gate in scenarios where the desired outcome is the negation of an OR operation. Essentially, a NOR gate is an OR gate followed by a NOT gate. It outputs true only when all inputs are false. This characteristic makes NOR gates particularly useful in situations where the circuit needs to inhibit an action unless all conditions are off. For instance, in a security system, a NOR gate could be used to keep an alarm silent unless all sensors are deactivated. NOR gates are also valued in digital logic design for their versatility as universal gates. They can be used to construct any other type of gate, making them essential in designs aiming to minimise the variety of components used. This is particularly beneficial in integrated circuit design, where reducing the variety of components can significantly impact manufacturing complexity and costs.

Determining the minimal number of gates required for a logic circuit involves a process known as minimisation. This process usually starts with the creation of a Boolean expression or a truth table representing the circuit's function. From there, Boolean algebra techniques, such as applying De Morgan's laws, distribution, and combining like terms, are used to simplify the expression. Additionally, Karnaugh maps (K-maps) are a visual tool that can be used to simplify Boolean expressions. They help identify common patterns or groups in the truth table, leading to simpler expressions that require fewer gates. It's also important to consider the use of universal gates like NAND and NOR, which can be configured to mimic the behaviour of any basic gate. By strategically using these gates, you can often reduce the overall gate count. The goal is to achieve the same logical function with a reduced number of gates, which not only saves space but also reduces power consumption and potential for errors in larger circuits.